Hierarchical task queues in shared-memory multiprocessor systems

Capacity Planning and Performance Monitoring

In Shared-Memory Multiprocessor Systems -- Hierarchical Task Queue (Serrazi, 2007) a series of simulations are completed on shared-memory multiprocessors that replicate the performance of parallel processing systems. The series of simulations look to replicate the results of computing resource allocation to the memory and processor level in a central, distributed and hierarchically-derived application and memory usage architecture (Serrazi, 2007). The study concludes that the hierarchical approach is the best choice, given shared memory performance, compensating for load imbalance of task queues. Overall, the simulation achieves its stated purpose and accurately fulfills the simulation objectives.

Suggested Improvements To the Study

The methodology of the simulation nearly guarantees that hierarchal-driven performance will be the best possible outcome given the share memory multiprocessor configuration to load balancing and tasks queues. A hierarchical organizational structure also allows for a specifically greater level of precision on load balancing across a wide variety of options.

Second, the variation in processor speeds and cache levels, bus speeds and command statements needs to be more varied to effectively test the conclusions to a greater level. This first simulation result indicates that the shared memory processor configuration is effectively defining distributed and central workflows or organizational structures are not as optimal. Yet upon closer analysis of the results, the tests appear one-dimensional and need greater levels of clarity and more testing of what would be considered exogenous variables. All of these factors taken together show that another series of simulations needs to be run in order to draw the conclusion of hierarchical performance is the best possible scenario.

Third, there is no variation in the type of data in the data packets, no inclusion or exclusion of randomness in data traffic speed and availability of data interruptions. In short, the simulation lacks the randomness in workflows that actual usage of this dual processor configuration would encounter over the long-term. As a result, the performance of these simulations must be taken in that context, mindful of the limitations they have.

Potential Uses of this Simulation