Computer Technology Assessing the Evolution

Computer Technology

Assessing the Evolution of Computer Technology

The advent of the reduced instruction set (RISC) microprocessor and memory platforms set the foundation for exponential increases in processor and memory performance over the last twenty-five years. The previous generation complex instruction set computer (CISC) series of algorithms and memory management approaches set constraints on processing power that did not fully take advantage of the available computing hardware at the time. With RISC-based approaches to microprocessor and memory design, the everyday concepts of virtual memory mapping, pre-emptive and cooperative multitasking, and the rapid gains in virtual memory performance are all being driven by the lessons learned in RISC programming and development. RISC microprocessor development has also led to the development of the dual core technologies (Vanhaverbeke, Noorderhaven, 2001) that Intel has continued to aggressively pursue as part of their product development strategies. In short, the lessons learned over twenty five years of RISC-based memory and microprocessor development are having a significant effect on the development of this and future generations of microprocessors and memory.

RISC Processor Assessment

The original design objective of RISC-based microprocessors centered on the need for more efficient telephone switching systems that could manage a greater number of calls and scale to support thousands of more users over time while keeping the fidelity of the signal constant (Vanhaverbeke, Noorderhaven, 2001). IBM was able to accomplish this on their Advanced Computing System (ACS0 and Model 801 processors. RISC-based instruction sets in these initial microprocessors led to the proliferation of first the IBM RT processor and next multiple product generations of the PowerPC processor. IBM widely evangelized the RISC-based electronics standard and was successful with design-in cycles on Smart Cards (Grossschadl, 2003) and third party PCs and storage systems (Deng, 2008).

RISC processors were able to deliver performance levels superior to the Motorola 68000 Series of processors and their dominant competitor at the time, Intel and their Pentium processors (Vanhaverbeke, Noorderhaven, 2001). IBM partnered with Motorola on the PowerPC processor development and further extended the RISC instruction set to integrate memory performance in real-time which was a major breakthrough at the time compared to Intel's approach to treating memory allocation purely at the register level instead of at the bus level (Vanhaverbeke, Noorderhaven, 2001). Another significant advance was made with IBM and Motorola working together, and that was the ability to create a configurable RISC-based microprocessor tailored to the specific needs of a given application area (Chen, Maskell, 2007). In conjunction with run-time checks and validity of memory performance and accuracy, the RISC processor was setting a rapid pace of innovation relative to Intel in the high-end processor market where the company was developing 64-bit and 128-bit microprocessors for highly specialized applications (Biswas, Carley, Simpson, Middha, Barua, 2006). The real-time integration to memory management that would lead to rapid advanced in superscalar memory management made possible with RISC-based microprocessors and memory however continued to be driven by IBM and their partners working in conjunction with each other on new developments (Biswas, Carley, Simpson, Middha, Barua, 2006).

Implications of RISC Development on Memory Management Advances