The evolution of RISC microprocessors and memory performance

Computer Technology

Assessing the Evolution of Computer Technology

The advent of the reduced instruction set (RISC) microprocessor and memory platforms set the foundation for exponential increases in processor and memory performance over the last twenty-five years. The previous generation complex instruction set computer (CISC) series of algorithms and memory management approaches set constraints on processing power that did not fully take advantage of the available computing hardware at the time. With RISC-based approaches to microprocessor and memory design, the everyday concepts of virtual memory mapping, pre-emptive and cooperative multitasking, and the rapid gains in virtual memory performance are all being driven by the lessons learned in RISC programming and development. RISC microprocessor development has also led to the development of the dual core technologies (Vanhaverbeke, Noorderhaven, 2001) that Intel has continued to aggressively pursue as part of their product development strategies. In short, the lessons learned over twenty five years of RISC-based memory and microprocessor development are having a significant effect on the development of this and future generations of microprocessors and memory.

Implications of RISC Development on Memory Management Advances

Over the first twenty five years of RISC processor and memory development the key lessons learned in processor-to-memory integration led to breakthroughs including how to make multithreading for 32-bit and higher bit order applications collaborate in memory, how to minimize cycle time and increase cache memory predictability over time (Biswas, Carley, Simpson, Middha, Barua, 2006). Cycle times and cache memory became and still are the two most monitored key performance indicators (KPIs) of system performance in systems due to the progression made in RISC-to-memory integration (Vanhaverbeke, Noorderhaven, 2001). Superscalar memories today reflect the decades of lessons learned with from RISC-based microprocessor development, specifically how to translate multiple memory calls into a single command. Superscalar and pipelining approaches to memory management capitalize on reduced instruction sets of optimize performance by minimizing interrupt calls. The lessons learned from RISC processors are today also reflected in virtualization algorithms used for managing complexes or segments of servers used for running Google and other search-intensive applications as well. Virtualization also has made real-time memory management possible for creating multitenant-based Software-as-a-Service (SaaS) applications (Biswas, Carley, Simpson, Middha, Barua, 2006). The use of RISC-based approaches to managing memory and the progression from superscalar and pre-emptive multitasking and virtualization of memory management algorithms (Biswas, Carley, Simpson, Middha, Barua, 2006) has also led to advances in security of systems and memory as well. Multi-threaded applications based on the Win32 Application Programming Interface (API) for example have significant security advantages over previous generation shared or collative approaches to managing memory. The progression to multithreaded applications has led to significantly greater levels of security as a result (Biswas, Carley, Simpson, Middha, Barua, 2006).